MRM is an attractive memory technology, offering non-volatility, high performance, and high endurance. MRM structures include, for example, spin torque-transfer magneto-resistive random access memory (STT-MRAM), voltage-controlled magnetic anisotropy magneto-resistive random access memory (VCMA-MRAM), and spin orbit torque magneto-resistive random access memory (SOT-MRAM), among others known in the art. Regardless of the specific type, and with reference to FIG. 1, an MRM cell 100 includes an MRM magnetic tunnel junction (MTJ) 101 in series with an MRM field effect transistor (FET) 102 (hereinafter MRM transistor 103). The MRM MTJ 101 includes a magnetic fixed or pinned layer 111, which is a permanent magnet set to a particular polarity, a magnetic free layer 112, which has a changeable polarity, and tunnel barrier layer 113 separating the fixed layer 111 and the free layer 112. When the MRM MTJ 101 is in a parallel state (both layers 111 and 112 having the same polarity), the MRM cell 100 indicates a logic zero (0). When the MRM MTJ 101 is in an anti-parallel state (layers 111 and 112 having opposite polarity), the MRM cell 100 indicates a logic one (1). The MRM transistor 102 includes a semiconductor substrate 121, ion-doped MRM source and drain regions 122, 123 disposed in the substrate 121, and a conductive gate electrode 124 overlying the substrate 121 between the MRM source and drain regions 122, 123. A control voltage applied to the gate electrode 124 controls the flow of current through an underlying channel 125 between the MRM source and drain regions 122, 123.
The control voltage is applied to the gate electrode 124 by a word line (WL) 131. A source line (SL) 132 is electrically connected to the MRM source region 122. A bit line (BL) 133 is electrically connected to the MRM MTJ 101, which in turn is electrically connected to the MRM drain region 123. In a memory array on an integrated circuit, the SL 132 may be so connected to a plurality of MRM transistors 102, and the BL 133 may be so connected to a plurality of MRM MTJs 101. One memory cell 100 along the BL 133 is selected by turning on its WL 131. When a relatively large voltage (e.g., about 400 mV or greater) is forced across the cell 100 from BL 133 to SL 132, the selected cell's MTJ 101 is written into a particular state, which is determined by the polarity of this voltage (BL 133 high vs. SL 132 high). When the cell 100 is in the logic zero (0) or parallel state, its MTJ resistance (R0) is lower than when the cell 100 is in the logic one (1) or antiparallel state (R1). A selected cell 100 may be read by sensing the resistance from BL 133 to SL 132. The “sense” or “read” voltage may be, in some devices, lower than the write voltage in order to distinguish write and read operations, and to avoid inadvertently disturbing the cell 100 during a read operation, although it need not be lower in other devices. However, random device variations (e.g., dimensions and other parameters) may lead to corresponding variations in R0 and R1. Thus, for some MRM MTJs 101, the actual distributions of R0 and R1 for a particular device may in practice overlap. In this case, it may be difficult to accurately read the state of the memory cell 100.
Accordingly, it is desirable to provide MRM structures with improved sensing at low read voltages, and associated sensing methods. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.